GitHub

RISC-V Single Cycle Processor on Basys 3 FPGA

This project presents the design and implementation of a 32-bit Single Cycle RISC-V Processor using Verilog HDL. The processor supports the core RV32I instruction set, including arithmetic, logical, ...
GitHub

FPGA MNIST Vision Transformer (ViT) — Basys 3 / Artix-7

A personal hobby project exploring an end-to-end training-to-silicon flow for a small Vision Transformer. This repository contains a synthesizable Vision Transformer (ViT) inference accelerator ...
IEEE

Design and Implementation of 5-Stage Pipelined RISC-V Processor on FPGA

Abstract: This paper presents the design and implementation of a 32-bit, in-order, 5-stage pipelined RISC-V processor, executed on the Basys 3 Artix-7 FPGA. RISC-V, an open-source Instruction Set ...
IEEE

FPGA Based AI Inference Accelerator for Low-End Embedded Systems

Aim: This research aims to develop a hardware accelerator to inference AI models for low-end embedded platforms using FPGAs as they are reconfigurable, have parallel and real-time processing ...